1. Field of the Invention
Example embodiments of the present invention relate generally to a semiconductor memory test device and method thereof, and more particularly to a semiconductor memory test device and method of testing a semiconductor memory device with the semiconductor memory test device.
2. Description of the Related Art
A memory test may typically include a wafer test executed in a wafer stage before a fabrication process and a package test executed in a package stage after the fabrication process. The wafer test may include a pre-laser test executed before a laser repair process and an electronic die sorting (EDS) test executed after the laser repair process. A die passing the EDS test may be manufactured into a package memory through the fabrication process.
The wafer test may be performed in the wafer state. The wafer test may be performed so as to detect failed dyes for which additional processes are performed before manufacturing the dyes into packages. Further, the wafer test may increase a yield of manufactured devices because at least a portion of the failed dyes may be repaired after failure detection.
Conventional memory devices may include redundant cells. If the memory device has one or more failed cells, the memory device may replace the failed cells with the redundant cells (hereinafter referred to as a “repair operation”). The repair operation may be based upon determining which memory cell within the memory device is a failed cell. The pre-laser test may be performed before the laser repair (e.g., the repair operation), and as such, the pre-laser may locate positions of the failed cell(s).
The pre-laser test may generate a bit-map. The bit-map may include a logical bit-map indicating locations of failed cells to logical addresses and a physical bit-map indication locations of failed cells to where the cells may physically positioned on the memory device. Here, the physical bit-map may typically be used in the wafer test.
In the physical bit-map, the logical addresses may be adjusted based on a mode of operation of the memory device (e.g., a test mode). External addresses may differ from the physical addresses corresponding to the actual cell arrangement of the memory device. Such a difference may result from a difference between the physical and logical addresses of the memory cells. The physical addresses may be changed based upon an input/output (I/O) size of the memory device. For example, if the I/O size corresponds to ‘1,’ the logical addresses may be the same as the physical addresses. If the I/O size corresponds to ‘2,’ the logical addresses may require an extra bit for discriminating between the different addresses, and so on.
Generally, conventional semiconductor memory devices may have configurations such as x2, x4, x8, x16 or x32 (e.g., I/O ratios of logical to physical addresses) of output bits in one cycle based on usage. For example, in a dynamic random access memory (DRAM) with 16 megabytes (MBs) of storage, a configuration of the DRAM may be 16 MB×1, 4 MB×4, 2 MB×8 or 1 MB×16. Here, the 16 MB×1 configuration may indicate a memory including 16 MB of 1-bit data, and the 4 MB×4 configuration may indicate a memory, including 4 MB of 4-bit data, the 2 Mb×8 configuration may indicate a memory including 2 MB of 8-bit data and the 1 MB×16 may indicate a memory including 1 MB of 16-bit data. 16 MB memory cells may be integrated on a single chip in each of the above-described configurations.
With respect to an address usage, the configurations may be partitioned based upon column address usage. With regard to a structure of the memory device, bonding pads may be used distinguish the respective configurations (e.g., x16, x8, x4, etc.) and the memory device may be packaged.
In a conventional package structure, in an example, if the memory device is packaged comply with the x16 configuration, the memory may not thereafter be adjusted to another configuration (e.g., into the x8 configuration). Because conventional semiconductor memory device may be adapted to conform with different configurations based upon different manufacturing requirements, tests may be performed based upon which configuration is established for the semiconductor memory device. As discussed above, a memory configuration (e.g., x2, x4, x8, etc.) for a conventional semiconductor memory device may typically be determined once the semiconductor memory device has been packaged (e.g., in a package level). Accordingly, a mode test may be executed at the package level of a fabrication of a conventional semiconductor memory device.
At the package level, tests may be performed on wafer products and multi-chip package products. In addition, while performing the wafer test, articles used in the package test may be processed along with articles used in the wafer test (hereinafter referred to as a “mixed test”). The pre-laser test in the mixed test may experience a number of problems, such as a position of the test article in a program, a method of handling failed bit information, a complex operation of the repair operation, etc.
FIG. 1 is a schematic diagram illustrating a conventional semiconductor memory test device. Referring to FIG. 1, a device under test (DUT) (not shown) may be connected to a tester in the conventional semiconductor memory test device. In the tester, a data selector 1 may receive fail information FAIL of data bits from a logic comparator (not shown). The logic comparator may compare data from the DUT with expected data generated by an algorithmic pattern generator (ALPG).
Referring to FIG. 1, the tester may include the data selector 1, a data formatter 2, an address selector 3, an address formatter 4 and a decoder 5. The data selector 1 may receive pass/fail information FAIL from the logic comparator to output handled data. The data formatter 2 may reorder the handled data from the data selector 1 to a given order by an ordering process based on given values. The address selector 3 may handle addresses ADDRESS from an address generator (not shown) to output handled addresses. The address formatter 4 may reorder the handled addresses from the address selector 3 to a given order by an ordering process based on given values. The decoder 5 may adjust a configuration (e.g., x2, . . . , x16) of a memory under test based upon usage (e.g., column usage).
Referring to FIG. 1, the ordering process of the address formatter 4 and/or the data formatter 2 may be based upon an order of pins during data input/output. The ordering process may include a sequential addressing process and an interleaved addressing process, each of which may be defined within well-known joint electronic device engineering council (JEDEC) protocols.
Referring to FIG. 1, in an example, data may be ordered as [0,1,2,3], [2,3,0,1], [1,2,3,0], [2,3,1,0], [3,0,1,2], etc., by the sequential addressing process. If a standard of a fail memory 10 is fixed, the fail memory 10 may have an unchangeable structure.
The structure may be “unchangeable” or fixed because signals of the decoder 5 may have a fixed format such that fail information may be addressed in the same manner. Therefore, a fail address may be incorrectly assigned due to a mismatching between areas of the memory under test and the fail memory if a test mode or memory configuration is changed. Thus, for example, if the memory under test changes from a x2 memory address protocol to an x8 memory address protocol for logical to physical address mapping. In addition, if the test mode or memory address protocol is changed, a program to adjust the standard of the memory configuration of the fail memory may be relatively complex and expensive.